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CODES
2010
IEEE
14 years 7 months ago
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
Yosi Ben-Asher, Nadav Rotem
SIGARCH
2010
89views more  SIGARCH 2010»
14 years 4 months ago
Efficient reconfigurable design for pricing asian options
Arithmetic Asian options are financial derivatives which have the feature of path-dependency: they depend on the entire price path of the underlying asset, rather than just the in...
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, ...
SIGCOMM
2010
ACM
14 years 9 months ago
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
We present SwitchBlade, a platform for rapidly deploying custom protocols on programmable hardware. SwitchBlade uses a pipeline-based design that allows individual hardware module...
Muhammad Bilal Anwer, Murtaza Motiwala, Muhammad M...
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
15 years 4 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
INFOCOM
2010
IEEE
14 years 7 months ago
FlashTrie: Hash-based Prefix-Compressed Trie for IP Route Lookup Beyond 100Gbps
It is becoming apparent that the next generation IP route lookup architecture needs to achieve speeds of 100Gbps and beyond while supporting both IPv4 and IPv6 with fast real-time ...
Masanori Bando, H. Jonathan Chao