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» Pipelined Memory Shared Buffer for VLSI Switches
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CODES
2006
IEEE
15 years 3 months ago
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
15 years 6 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
15 years 1 months ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
SIGMOD
2005
ACM
138views Database» more  SIGMOD 2005»
15 years 9 months ago
QPipe: A Simultaneously Pipelined Relational Query Engine
Relational DBMS typically execute concurrent queries independently by invoking a set of operator instances for each query. To exploit common data retrievals and computation in con...
Stavros Harizopoulos, Vladislav Shkapenyuk, Anasta...
ISPASS
2009
IEEE
15 years 4 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...