Sciweavers

417 search results - page 31 / 84
» Pipelining in Multi-Query Optimization
Sort
View
CGO
2003
IEEE
15 years 5 months ago
Optimizing Memory Accesses For Spatial Computation
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...
Mihai Budiu, Seth Copen Goldstein
HPCA
2004
IEEE
16 years 6 days ago
Creating Converged Trace Schedules Using String Matching
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
Satish Narayanasamy, Yuanfang Hu, Suleyman Sair, B...
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 5 months ago
Parallel subdivision surface rendering and animation on the Cell BE processor
—Subdivision Surfaces provide a compact way to describe a smooth surface using a mesh model. They are widely used in 3D animation and nearly all modern modeling programs support ...
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Ben...
TC
2010
14 years 6 months ago
Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
Tweakable enciphering schemes are length preserving block cipher modes of operation that provide a strong pseudo-random permutation. It has been suggested that these schemes can b...
Cuauhtemoc Mancillas-López, Debrup Chakrabo...
MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
15 years 3 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...