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FSE
2005
Springer
112views Cryptology» more  FSE 2005»
15 years 5 months ago
How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4 Processors
Abstract. This paper discusses the state-of-the-art software optimization methodology for symmetric cryptographic primitives on Pentium III and 4 processors. We aim at maximizing s...
Mitsuru Matsui, Sayaka Fukuda
ESTIMEDIA
2004
Springer
15 years 5 months ago
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
Tien-Wei Hsieh, Youn-Long Lin
FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 5 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
LCTRTS
2001
Springer
15 years 4 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
75
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CLUSTER
2000
IEEE
15 years 4 months ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada