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» Pipelining in Multi-Query Optimization
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DATE
2000
IEEE
89views Hardware» more  DATE 2000»
15 years 4 months ago
A System-Level Synthesis Algorithm with Guaranteed Solution Quality
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Ch...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 3 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
LCTRTS
2007
Springer
15 years 5 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
103
Voted
DAC
2003
ACM
16 years 22 days ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
81
Voted
ICDE
2010
IEEE
200views Database» more  ICDE 2010»
15 years 6 months ago
GenerIE: Information extraction using database queries
— Information extraction systems are traditionally implemented as a pipeline of special-purpose processing modules. A major drawback of such an approach is that whenever a new ex...
Luis Tari, Phan Huy Tu, Jörg Hakenberg, Yi Ch...