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» Pipelining in Multi-Query Optimization
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CF
2010
ACM
15 years 4 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
ICS
2010
Tsinghua U.
15 years 4 months ago
Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping
Because of their tremendous computing power and remarkable cost efficiency, GPUs (graphic processing unit) have quickly emerged as an influential computing platform for a broad ...
Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Xipeng She...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 4 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
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ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
15 years 3 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 3 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin