5216 search results - page 242 / 1044 » Planning as Model Checking |
133
click to vote
ENTCS
2007
15 years 4 months ago
2007
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
123
click to vote
GLVLSI
2003
IEEE
15 years 9 months ago
2003
IEEE
A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but ...
146
click to vote
ICSE
1999
IEEE-ACM
15 years 8 months ago
1999
IEEE-ACM
In this paper we show how the FLAVERS data flow analysis technique, originally formulated for programs with the rendezvous model of concurrency, can be applied to concurrent Java...
133
click to vote
FMCAD
2009
Springer
15 years 8 months ago
2009
Springer
This paper discusses a methodology used on an industrial hardware development project to validate various cache-coherence protocol components. The idea is to use a high level model...
133
click to vote
ATAL
2009
Springer
15 years 5 months ago
2009
Springer
Motion planning for mobile agents, such as robots, acting in the physical world is a challenging task, which traditionally concerns safe obstacle avoidance. We are interested in p...