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» Platform modeling for exploration and synthesis
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VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
15 years 10 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
APN
2007
Springer
15 years 4 months ago
A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms
Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In previous work, an automatic ...
Kyller Costa Gorgônio, Jordi Cortadella, Fei...
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 1 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
15 years 6 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
15 years 1 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...