351 search results - page 26 / 71 » Plug-and-Play Architectural Design and Verification |
DAC
2007
ACM
15 years 10 months ago
2007
ACM
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
DAC
2010
ACM
15 years 1 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
DAC
1990
ACM
15 years 1 months ago
1990
ACM
In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the ne...
ASYNC
2007
IEEE
15 years 1 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...