This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to ...