351 search results - page 30 / 71 » Plug-and-Play Architectural Design and Verification |
107
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EUROMICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
VLSID
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
156
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SIGMOD
2005
ACM
15 years 10 months ago
2005
ACM
Significant efforts are currently invested in application integration to enable the interaction and composition of business processes of different companies, yielding complex, mul...
ISARCS
2010
14 years 11 months ago
2010
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...