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117
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DATE
2010
IEEE
140views Hardware» more  DATE 2010»
15 years 7 months ago
Variation-aware interconnect extraction using statistical moment preserving model order reduction
—1 In this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It...
Tarek A. El-Moselhy, Luca Daniel
ICRA
2007
IEEE
117views Robotics» more  ICRA 2007»
15 years 8 months ago
Integration of Coordination Mechanisms in the BITE Multi-Robot Architecture
— Recent years are seeing a renewed interest in general multi-robot architectures, capable of automating coordination. However, few architectures explore integration of multiple ...
Gal A. Kaminka, Inna Frenkel
FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 5 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
IC
2001
15 years 3 months ago
The SMART Project Exploiting the Heterogeneous Mobile World
The wide proliferation of wireless systems and the use of software radio technologies enables the employment of a heterogeneous network. In this concept services are delivered via...
Paul J. M. Havinga, Gerard J. M. Smit, Lars Kristi...
ALGORITHMICA
2006
96views more  ALGORITHMICA 2006»
15 years 1 months ago
Canonical Forms and Algorithms for Steiner Trees in Uniform Orientation Metrics
We present some fundamental structural properties for minimum length networks (known as Steiner minimum trees) interconnecting a given set of points in an environment in which edg...
Marcus Brazil, D. A. Thomas, J. F. Weng, Martin Za...