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173
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ARITH
2005
IEEE
16 years 1 months ago
2005
IEEE
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
190
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ASYNC
2002
IEEE
16 years 13 days ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
191
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FCCM
2004
IEEE
15 years 11 months ago
2004
IEEE
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation...
177
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FPL
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. This paper presents a new data representation known as Dual FiXedpoint (DFX), which employs a single bit exponent to select two different fixedpoint scalings. DFX provide...