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VLSI
2005
Springer
15 years 8 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
112
Voted
TVLSI
2008
121views more  TVLSI 2008»
15 years 2 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
137
Voted
LICS
2010
IEEE
15 years 12 days ago
Fixed-Point Definability and Polynomial Time on Graphs with Excluded Minors
We prove that fixed-point logic with counting captures polynomial time on all classes of graphs with excluded minors. That is, for every class C of graphs such that some graph H is...
Martin Grohe
118
Voted
SIGSOFT
2004
ACM
16 years 3 months ago
PSE: explaining program failures via postmortem static analysis
In this paper, we describe PSE (Postmortem Symbolic Evaluation), a static analysis algorithm that can be used by programmers to diagnose software failures. The algorithm requires ...
Roman Manevich, Manu Sridharan, Stephen Adams, Man...
109
Voted
EMSOFT
2007
Springer
15 years 8 months ago
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
Software components are modular and can enable post-deployment update, but their high overhead in runtime and memory is prohibitive for many embedded systems. This paper proposes ...
Jiwon Hahn, Pai H. Chou