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ERSA
2010
137views Hardware» more  ERSA 2010»
14 years 9 months ago
An Automated Scheduling and Partitioning Algorithm for Scalable Reconfigurable Computing Systems
As reconfigurable computing (RC) platforms are becoming increasingly large-scale and heterogeneous, efficiently scheduling and partitioning applications on these platforms is a gro...
Casey Reardon, Alan D. George, Greg Stitt, Herman ...
ERSA
2010
199views Hardware» more  ERSA 2010»
14 years 9 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
ISLPED
2010
ACM
231views Hardware» more  ISLPED 2010»
14 years 12 months ago
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero bo...
Yibo Chen, Jishen Zhao, Yuan Xie
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
14 years 11 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
15 years 4 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee