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» Posix: A Model for Future Computing
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ICS
2010
Tsinghua U.
15 years 7 months ago
Non-Malleable Codes
We introduce the notion of "non-malleable codes" which relaxes the notion of error-correction and errordetection. Informally, a code is non-malleable if the message cont...
Stefan Dziembowski, Krzysztof Pietrzak, Daniel Wic...
PPOPP
2010
ACM
15 years 4 months ago
Thread to strand binding of parallel network applications in massive multi-threaded systems
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
15 years 3 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
81
Voted
ESA
2007
Springer
176views Algorithms» more  ESA 2007»
15 years 3 months ago
Arrangements in Geometry: Recent Advances and Challenges
We review recent progress in the study of arrangements in computational and combinatorial geometry, and discuss several open problems and areas for further research. In this talk I...
Micha Sharir
79
Voted
CASES
2006
ACM
15 years 3 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh