Sciweavers

60 search results - page 10 / 12
» Post-Silicon Debug Using Programmable Logic Cores
Sort
View
IEEEPACT
2005
IEEE
15 years 3 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
ICSE
2010
IEEE-ACM
14 years 11 months ago
DETERMIN: inferring likely deterministic specifications of multithreaded programs
The trend towards multicore processors and graphic processing units is increasing the need for software that can take advantage of parallelism. Writing correct parallel programs u...
Jacob Burnim, Koushik Sen
80
Voted
CODES
1999
IEEE
15 years 1 months ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
EH
1999
IEEE
161views Hardware» more  EH 1999»
15 years 1 months ago
Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
John F. McDonald, Bryan S. Goda
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 3 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin