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ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 4 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
ICDCSW
2000
IEEE
15 years 4 months ago
Enabling Flexible QoS Support in the Object Request Broker COOL
Support of end-to-end Quality-of-Service (QoS) and ate high-level programming abstractions are two crucial factors for the development of future telecommunication services and dis...
Tom Kristensen, Thomas Plagemann
ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 4 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
MSS
2000
IEEE
72views Hardware» more  MSS 2000»
15 years 4 months ago
The InTENsity PowerWall: A Case Study for a Shared File System Testing Framework
The InTENsity PowerWall is a display system used for high-resolution visualization of very large volumetric data sets. The display is linked to two separate computing environments...
Alex W. Elder, Thomas Ruwart, Benjamin D. Allen, A...
ISSTA
2000
ACM
15 years 4 months ago
Which pointer analysis should I use?
During the past two decades many di erent pointer analysis algorithms have been published. Although some descriptions include measurements of the e ectiveness of the algorithm, qu...
Michael Hind, Anthony Pioli