178 search results - page 15 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
ASPDAC
2009
ACM
15 years 5 months ago
2009
ACM
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
ASPDAC
1995
ACM
15 years 2 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
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LCTRTS
2010
Springer
14 years 8 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
MICRO
2005
IEEE
15 years 4 months ago
2005
IEEE
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
ICCAD
1995
IEEE
15 years 2 months ago
1995
IEEE
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...