178 search results - page 24 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
ASPDAC
2008
ACM
15 years 17 days ago
2008
ACM
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
DSD
2010
IEEE
14 years 8 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
122
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ICDE
2012
IEEE
13 years 1 months ago
2012
IEEE
—With the exponential growth in the amount of data that is being generated in recent years, there is a pressing need for applying machine learning algorithms to large data sets. ...
127
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PLDI
1999
ACM
15 years 2 months ago
1999
ACM
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
DATE
2010
IEEE
15 years 3 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...