178 search results - page 26 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
DAC
1995
ACM
15 years 2 months ago
1995
ACM
- We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either ...
IJCAI
1989
14 years 11 months ago
1989
Inducing disjunctive and iterative macro-operators from empirical problem-solving traces provides a more powerful knowledge compilation method than simple linear macro-operators. ...
LCTRTS
2004
Springer
15 years 3 months ago
2004
Springer
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded ...
ASPDAC
2007
ACM
15 years 2 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
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EUROPAR
2010
Springer
14 years 11 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...