178 search results - page 2 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
109
Voted
ISCAS
1999
IEEE
15 years 4 months ago
1999
IEEE
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
114
click to vote
DAC
2003
ACM
16 years 1 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
119
Voted
ASAP
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
IEEEINTERACT
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper examines the effect of compiler optimizations on the energy usage and power consumption of the Intel Pentium 4 processor. We measure the effects of different levels of ...
71
Voted
DAC
2000
ACM
16 years 1 months ago
2000
ACM
