Sciweavers

178 search results - page 8 / 36
» Power Compiler: A Gate-Level Power Optimization and Synthesi...
Sort
View
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 2 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
95
Voted
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
14 years 8 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
71
Voted
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
15 years 4 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 2 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
DATE
2002
IEEE
153views Hardware» more  DATE 2002»
15 years 3 months ago
Low Power Embedded Software Optimization Using Symbolic Algebra
The market demand for portable multimedia applications has exploded in the recent years. Unfortunately, for such applications current compilers and software optimization methods o...
Armita Peymandoust, Tajana Simunic, Giovanni De Mi...