Sciweavers

1419 search results - page 128 / 284
» Power Droop Testing
Sort
View
114
Voted
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
15 years 8 months ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
118
Voted
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
15 years 8 months ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
149
Voted
IBPRIA
2003
Springer
15 years 8 months ago
Underwater Cable Tracking by Visual Feedback
Nowadays, the surveillance and inspection of underwater installations, such as power and telecommunication cables and pipelines, is carried out by trained operators who, from the s...
Javier Antich, Alberto Ortiz
ISLPED
1996
ACM
93views Hardware» more  ISLPED 1996»
15 years 7 months ago
250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies
This paper describes a family of high-speed Finite Impulse Response (FIR) digital filters that have been scaled across three generations of CMOS processes. The processes include c...
Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Ge...
127
Voted
CAV
2010
Springer
187views Hardware» more  CAV 2010»
15 years 7 months ago
Fences in Weak Memory Models
We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter- and intra-pr...
Jade Alglave, Luc Maranget, Susmit Sarkar, Peter S...