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LCTRTS
2007
Springer
15 years 6 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
101
Voted
IJHPCA
2006
122views more  IJHPCA 2006»
15 years 13 days ago
A New Hardware Monitor Design to Measure Data Structure-Specific Cache Eviction Information
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
Bryan R. Buck, Jeffrey K. Hollingsworth
98
Voted
DAC
2000
ACM
16 years 1 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
ICS
1995
Tsinghua U.
15 years 4 months ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...
CODES
2005
IEEE
15 years 2 months ago
Automated data cache placement for embedded VLIW ASIPs
Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficie...
Paul Morgan, Richard Taylor, Japheth Hossell, Geor...