Sciweavers

446 search results - page 24 / 90
» Power Efficient Mediaprocessors: Design Space Exploration
Sort
View
126
Voted
VLSISP
2011
216views Database» more  VLSISP 2011»
14 years 8 months ago
Accurate Area, Time and Power Models for FPGA-Based Implementations
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
Lanping Deng, Kanwaldeep Sobti, Yuanrui Zhang, Cha...
CCR
2008
88views more  CCR 2008»
15 years 1 months ago
Rethinking virtual network embedding: substrate support for path splitting and migration
Network virtualization is a powerful way to run multiple architectures or experiments simultaneously on a shared infrastructure. However, making efficient use of the underlying re...
Minlan Yu, Yung Yi, Jennifer Rexford, Mung Chiang
105
Voted
ASAP
2010
IEEE
185views Hardware» more  ASAP 2010»
15 years 2 months ago
ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors
Abstract—The demand for biomedical implants keeps increasing. However, most of the current implant design methodologies involve custom-ASIC design. The SiMS project aims to chang...
Dhara Dave, Christos Strydis, Georgi Gaydadjiev
RSP
2003
IEEE
147views Control Systems» more  RSP 2003»
15 years 7 months ago
Cache Configuration Exploration on Prototyping Platforms
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
Chuanjun Zhang, Frank Vahid
133
Voted
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 7 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane