Sciweavers

446 search results - page 25 / 90
» Power Efficient Mediaprocessors: Design Space Exploration
Sort
View
DAC
2004
ACM
15 years 3 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
59
Voted
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 2 months ago
Enhanced Q-learning algorithm for dynamic power management with performance constraint
- This paper presents a novel power management techniques based on enhanced Q-learning algorithms. By exploiting the submodularity and monotonic structure in the cost function of a...
Wei Liu, Ying Tan, Qinru Qiu
IPPS
2006
IEEE
15 years 3 months ago
Parallel morphological processing of hyperspectral image data on heterogeneous networks of computers
Recent advances in space and computer technologies are revolutionizing the way remotely sensed data is collected, managed and interpreted. The development of efficient techniques ...
Antonio J. Plaza
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 2 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
106
Voted
DAC
2009
ACM
15 years 10 months ago
Exploring serial vertical interconnects for 3D ICs
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
Sudeep Pasricha