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» Power Efficient Mediaprocessors: Design Space Exploration
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ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 3 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
DATE
2003
IEEE
118views Hardware» more  DATE 2003»
15 years 3 months ago
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs
This paper details the first step of the Design Trotter framework for design space exploration applied to dedicated SOCs. The aim of this step is to provide metrics in order to gu...
Yannick Le Moullec, Nahla Ben Amor, Jean-Philippe ...
IEEEPACT
2002
IEEE
15 years 2 months ago
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, ...
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasu...
VLDB
1987
ACM
93views Database» more  VLDB 1987»
15 years 1 months ago
FAD, a Powerful and Simple Database Language
FAD is a powerful and simple language designed for a highly parallel database machine. The basic concepts of the language are its data structures (which we call objects) and its p...
François Bancilhon, Ted Briggs, Setrag Khos...
GECCO
2003
Springer
103views Optimization» more  GECCO 2003»
15 years 2 months ago
Evaluation of Parameter Sensitivity for Portable Embedded Systems through Evolutionary Techniques
Power consumption and portability issues are becoming increasingly significant in embedded system architectures. Therefore, it is important that chip architects and integrated circ...
James Northern III, Michael A. Shanblatt