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» Power Efficient Mediaprocessors: Design Space Exploration
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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 4 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
105
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FUNGAMES
2008
14 years 10 months ago
Test-Bed for Multimodal Games on Mobile Devices
We present a test-bed platform for the iterative design of multimodal games on a mobile phone or a PDA. While our test-bed platform is general to multimodal systems, in this paper ...
Marcello Coiana, Alex Conconi, Laurence Nigay, Mic...
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
15 years 3 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
SAC
2008
ACM
14 years 9 months ago
Expected energy consumption minimization in DVS systems with discrete frequencies
Energy-efficiency has been an important system issue in hardware and software designs to extend operation duration or cut power bills. This research explores systems with probabil...
Jian-Jia Chen
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
14 years 10 months ago
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...
Weixun Wang, Xiaoke Qin, Prabhat Mishra