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» Power Efficient Mediaprocessors: Design Space Exploration
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97
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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
JRTIP
2008
249views more  JRTIP 2008»
14 years 9 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
72
Voted
DATE
2006
IEEE
93views Hardware» more  DATE 2006»
15 years 3 months ago
Restructuring field layouts for embedded memory systems
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...
Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo...
HUC
2009
Springer
15 years 2 months ago
Applying pervasive technologies to create economic incentives that alter consumer behavior
Economic incentives are a powerful way of shaping consumer behavior towards more commercially efficient and environmentally sustainable patterns. In this paper, we explore the id...
Tetsuo Yamabe, Vili Lehdonvirta, Hitoshi Ito, Hayu...
MOBIQUITOUS
2007
IEEE
15 years 3 months ago
Battery-Aware Embedded GPS Receiver Node
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
Dejan Raskovic, David Giessel