1238 search results - page 208 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
MICRO
2000
IEEE
14 years 11 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
HPCA
2006
IEEE
16 years 1 days ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
134
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ECRTS
2007
IEEE
15 years 6 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
101
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APCSAC
2006
IEEE
15 years 5 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
SIGADA
2001
Springer
15 years 4 months ago
2001
Springer
The last years have seen an increasing, albeit restricted simulation of large-scale networks on shared memory parallel platforms. As the complexity of communication protocols and ...