1238 search results - page 210 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
117
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ICCD
2007
IEEE
15 years 3 months ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
117
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TVLSI
2008
14 years 11 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
DAC
2004
ACM
16 years 18 days ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
87
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DAC
2005
ACM
16 years 18 days ago
2005
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
105
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HPCA
2006
IEEE
16 years 14 hour ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...