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» Power Efficient Processor Architecture and The Cell Processo...
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104
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ERSA
2007
177views Hardware» more  ERSA 2007»
15 years 1 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
96
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DSD
2010
IEEE
141views Hardware» more  DSD 2010»
14 years 9 months ago
Adaptive Beamforming Using the Reconfigurable MONTIUM TP
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen ...
99
Voted
ICS
2005
Tsinghua U.
15 years 5 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
88
Voted
ICRA
2000
IEEE
136views Robotics» more  ICRA 2000»
15 years 4 months ago
Recent Progress in Local and Global Traversability for Planetary Rovers
Autonomous planetary rovers operating in vast unknown environments must operate efficiently because of size, power and computing limitations. Recently, we have developed a rover c...
Sanjiv Singh, Reid G. Simmons, Trey Smith, Anthony...
IPPS
1999
IEEE
15 years 3 months ago
Portable Parallel Programming for the Dynamic Load Balancing of Unstructured Grid Applications
The ability to dynamically adapt an unstructured grid (or mesh) is a powerful tool for solving computational problems with evolving physical features; however, an efficient parall...
Rupak Biswas, Leonid Oliker, Sajal K. Das, Daniel ...