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IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 5 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
IJCSA
2008
117views more  IJCSA 2008»
14 years 11 months ago
Altivec Vector Unit Customization for Embedded Systems
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...
Tarik Saidani, Joel Falcou, Lionel Lacassagne, Sam...
ISCAS
2003
IEEE
66views Hardware» more  ISCAS 2003»
15 years 4 months ago
A triple port RAM based low power commutator architecture for a pipelined FFT processor
This paper proposes a low power commutator architecture based on triple port RAMs rather than dual port RAMs or conventional FIFO.forthe radix-4 pipelined FFTprocessor implementat...
M. Hasan, Tughrul Arslan
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 4 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
15 years 4 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...