1238 search results - page 229 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
IPPS
2000
IEEE
15 years 3 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
107
click to vote
IPPS
1999
IEEE
15 years 3 months ago
1999
IEEE
In this paper we propose the use of an optical network not only as the communication medium, but also as a system-wide cache for the shared data in a multiprocessor. More specifica...
IPPS
1998
IEEE
15 years 3 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
ISCA
1997
IEEE
15 years 3 months ago
1997
IEEE
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
103
click to vote
CP
2006
Springer
15 years 3 months ago
2006
Springer
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...