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ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
15 years 5 months ago
Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video
Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell ...
Rafal Karakiewicz, Roman Genov
DAC
1999
ACM
16 years 17 days ago
Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
D. Allen, D. Behrends, B. Stanisic
VLSISP
2008
106views more  VLSISP 2008»
14 years 11 months ago
Architecture Considerations for Multi-Format Programmable Video Processors
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
Jonah Probell
IBMRD
2006
76views more  IBMRD 2006»
14 years 11 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
Nicholas P. Carter, Azmat Hussain
VLSID
2004
IEEE
122views VLSI» more  VLSID 2004»
15 years 12 months ago
A System Approach to Energy Management
: The accumulation of popular features in portable products such as mobile handsets is driving battery life to unacceptably low levels. Substantial change will not come from increm...
Dennis Monticelli