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ISLPED
1999
ACM
15 years 3 months ago
1999
ACM
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
99
Voted
TSP
2008
14 years 11 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
94
Voted
VLSID
2004
IEEE
15 years 12 months ago
2004
IEEE
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
HPCA
2005
IEEE
15 years 5 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
85
Voted
IPPS
2009
IEEE
15 years 6 months ago
2009
IEEE
In this paper, we present a methodology for profiling parallel applications executing on the IBM PowerXCell 8i (commonly referred to as the “Cell” processor). Specifically, we...