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IPPS
2010
IEEE
14 years 9 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...
99
Voted
PATMOS
2005
Springer
15 years 5 months ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
Fernando Castro, Daniel Chaver, Luis Piñuel...
92
Voted
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
16 years 3 days ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
DAC
2007
ACM
15 years 3 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae...
CF
2009
ACM
15 years 4 months ago
Data parallel acceleration of decision support queries using Cell/BE and GPUs
Decision Support System (DSS) workloads are known to be one of the most time-consuming database workloads that processes large data sets. Traditionally, DSS queries have been acce...
Pedro Trancoso, Despo Othonos, Artemakis Artemiou