Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...
Rafael H. Saavedra-Barrera, David E. Culler, Thors...
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
Abstract--Power density and heat density of multicore processor system are increasing exponentially with Moore's Law. High temperature on chip greatly affects its reliability,...