Sciweavers

1238 search results - page 57 / 248
» Power Efficient Processor Architecture and The Cell Processo...
Sort
View
IPPS
2008
IEEE
15 years 6 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 5 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...
IFIP
2001
Springer
15 years 4 months ago
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
: A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture...
Nuno Roma, Leonel Sousa
74
Voted
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
15 years 8 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 4 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson