1238 search results - page 60 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
ICPADS
2006
IEEE
15 years 5 months ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
199
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ICDE
2006
IEEE
16 years 1 months ago
2006
IEEE
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
102
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AFRICACRYPT
2010
Springer
15 years 6 months ago
2010
Springer
This paper describes an implementation of Pollard’s rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband En...
107
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MICRO
2010
IEEE
14 years 9 months ago
2010
IEEE
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...