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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 5 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
DAC
2008
ACM
16 years 24 days ago
Compiler-driven register re-assignment for register file power-density and temperature reduction
Temperature hot-spots have been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the ...
Xiangrong Zhou, Chenjie Yu, Peter Petrov
VLSISP
2008
132views more  VLSISP 2008»
14 years 11 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...
Brian M. H. Li, Philip Heng Wai Leong
CORR
2010
Springer
177views Education» more  CORR 2010»
14 years 9 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai
OPODIS
2008
15 years 1 months ago
Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms
Abstract Nowadays, most of the energy-aware real-time scheduling algorithms belong to the DVFS (Dynamic Voltage and Frequency Scaling) framework. These DVFS algorithms are usually ...
Joël Goossens, Dragomir Milojevic, Vincent N&...