1238 search results - page 76 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
IJCNN
2007
IEEE
15 years 6 months ago
2007
IEEE
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
MICRO
1999
IEEE
15 years 4 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
ASAP
2004
IEEE
15 years 3 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
ETFA
2008
IEEE
15 years 6 months ago
2008
IEEE
Power consumption and thermal problems limit the single-core processors to be faster. Processor architects are therefore moving toward multi-core processors. Developers of embedde...