1238 search results - page 78 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
ISSS
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
108
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ERSA
2008
15 years 1 months ago
2008
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...
103
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FPL
2010
Springer
14 years 9 months ago
2010
Springer
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
133
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ISCAPDCS
2008
15 years 1 months ago
2008
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...