Sciweavers

979 search results - page 114 / 196
» Power Macromodeling for High Level Power Estimation
Sort
View
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
14 years 12 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
MOBICOM
2010
ACM
14 years 10 months ago
CTRL: a self-organizing femtocell management architecture for co-channel deployment
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...
Ji-Hoon Yun, Kang G. Shin
ICIP
1999
IEEE
15 years 11 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
VLSID
2009
IEEE
107views VLSI» more  VLSID 2009»
15 years 10 months ago
Temperature Aware Scheduling for Embedded Processors
Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and inc...
Ramkumar Jayaseelan, Tulika Mitra
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 3 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy