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» Power Optimization in Current Mode Circuits
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ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
15 years 4 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
15 years 2 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...
77
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DAC
2006
ACM
15 years 10 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
VLSID
2010
IEEE
170views VLSI» more  VLSID 2010»
14 years 3 months ago
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Contro
The continuous increase of leakage power consumption in deep sub-micro technologies necessitates more aggressive leakage control. Runtime leakage control (RTLC) is effective, si...
Hao Xu, Wen-Ben Jone, Ranga Vemuri
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
15 years 10 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty