430 search results - page 34 / 86 » Power Optimized Combinational Logic Design |
123
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GLVLSI
1998
IEEE
15 years 5 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
106
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ISLPED
2003
ACM
15 years 6 months ago
2003
ACM
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
114
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ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
FCCM
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper introduces a design tool and its associated procedures for determining the sensitivity of outputs in a digital signal processing design to small errors introduced by ro...
128
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ECAI
2008
Springer
15 years 3 months ago
2008
Springer
Many real-world applications of AI require both probability and first-order logic to deal with uncertainty and structural complexity. Logical AI has focused mainly on handling com...