430 search results - page 41 / 86 » Power Optimized Combinational Logic Design |
150
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ARITH
2009
IEEE
15 years 11 months ago
2009
IEEE
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
188
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PPDP
2010
Springer
15 years 3 months ago
2010
Springer
This paperdescribes the use of a powerful graph query language for querying programs, and a novel combination of transformations for generating efficient implementations of the q...
127
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CF
2004
ACM
15 years 10 months ago
2004
ACM
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
156
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ICS
2005
Tsinghua U.
15 years 10 months ago
2005
Tsinghua U.
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
164
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DAC
2006
ACM
16 years 6 months ago
2006
ACM
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...