173 search results - page 10 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
ICCD
2002
IEEE
15 years 6 months ago
2002
IEEE
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
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APCCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...