173 search results - page 11 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
70
Voted
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters sel...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...
ITC
1989
IEEE
15 years 1 months ago
1989
IEEE
- The electrical effects of CMOS IC physical defects that caused stuck-openfaults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient re...